CTEC1631 Digital Signal Processing - 2007F

DSP Preparation Lab - Using the DSP Chip

In this lab, intended as an introduction to the DSP processor, you will use a dsPIC30F6012 DSP chip as a basic sampler.

Prelab

Download a copy of the dsPICDEM Users Guide #DS51425A from Microchip as well as the dsPIC30F6012 data sheet and programmer's reference manual.

Start with the SAMPLER.S program available on the home page. Build a project using the Project Wizard. Use the ASM-30 toolsuite built into MPLAB IDE, add the SAMPLER.S source file and be sure to include a linker ".gld" file for the 6012 processor available in the Program Files\Microchip\MPLAB ASM30 Suite\Support\gld directory. The project should now build properly.

Now, ensure the project works. Be sure to enable ICD-2 debugging by including the '__ICDRAM' definition in the source file as well as enabling DEBUG mode. To test the program, connect the input from the DSP board to an audio source (e.g. a Walkman^tm type device) via the 3.5mm stereo cable and connect the output to headphones or speakers. Set the output volume of the device reasonably loud (an amplitude of several volts peak-to-peak is best). When the program is running, sound should be heard clearly, when the program is stopped, sound will also cease (although small amounts of digital noise can likely be heard in the output - the analog filter will pick-up noise from the digital supply lines).

Sampling is accomplished using the on-chip ADC (input AN3) connected to LINE IN via the on-board anti-aliasing filter. An audio signal may be injected directly into the 3.5mm stereo input jack since the circuitry has a DC-isolator and re-biases the signal to be in the range 0 to 5V (see the circuit diagram for the board in the User's Guide). Playback is accomplished using the on-board MCP4101 digital pot (functioning as a DAC) connected to LINE OUT (via a reconstruction filter) which can drive a set of multimedia speakers or headphones directly.

Now, change the sample frequency by reducing the processor clock from 64MHz (4.00MHz * 16 PLL) to 4MHz (no PLL) as follows in the source code:

;       config __FOSC, CSW_FSCM_OFF & XT_PLL16  ;16xPLL - 120MHz/30MIPs at 7.37MHz XTAL
;       config __FOSC, CSW_FSCM_OFF & XT_PLL4   ;4xPLL
        config __FOSC, CSW_FSCM_OFF & XT

This change sets the sampling rate from 8KS/s to 2KS/s however the sampling and reconstruction filters both pass frequencies up to 4KHz so when run, an immense amount of aliasing should be heard in the output! Restore the clock frequency to 64MHz.

A further tutorial is available from the Microchip web site as outlined in the User's Guide, otherwise you may proceed to work on the moving average filter for lab #3.