LIBRARY ieee;
USE ieee.STD_LOGIC_1164.ALL;

ENTITY drill IS
	PORT(
		A, B, C, D		: IN 	STD_LOGIC;
		X, Y 			: OUT	STD_LOGIC);
END drill ;

ARCHITECTURE a OF drill IS
	SIGNAL input:  STD_LOGIC_VECTOR (3 DOWNTO 0);
	SIGNAL output: STD_LOGIC_VECTOR (1 DOWNTO 0);
BEGIN
 --  Concurrent Signal Assignment
 input (3) <= A;
 input (2) <= B;
 input (1) <= C;	
 input (0) <= D;

 --  Selected Signal Assignment
 WITH input SELECT
	output <= 	"00" WHEN "0000",
			"00" WHEN "0001",
			"00" WHEN "0010",
			"00" WHEN "0011",

			"00" WHEN "0100",
			"00" WHEN "0101",
			"00" WHEN "0110",
			"00" WHEN "0111",

			"00" WHEN "1000",
			"00" WHEN "1001",
			"00" WHEN "1010",
			"00" WHEN "1011",

			"00" WHEN "1100",
			"00" WHEN "1101",
			"00" WHEN "1110",
			"00" WHEN "1111",
			
			"00" WHEN others;

 X	<=	output(1);
 Y	<=	output(0);
 	
END a;