LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
ENTITY encoder IS
	PORT(
		nA1, nA2, nA3, nA4, nA5, nA6, nA7, nA8, nA9	: IN	STD_LOGIC;
		O0, O1, O2, O3					: OUT	STD_LOGIC);
END encoder;

ARCHITECTURE a OF encoder IS
	SIGNAL output: STD_LOGIC_VECTOR (3 DOWNTO 0);
BEGIN
  --  Conditional Signal Assignment
 encoder:
	output <= 		"1001" WHEN nA9='0' ELSE
				"1000" WHEN nA8='0' ELSE
				"0111" WHEN nA7='0' ELSE
				"0110" WHEN nA6='0' ELSE
				"0101" WHEN nA5='0' ELSE
				"0100" WHEN nA4='0' ELSE
				"0011" WHEN nA3='0' ELSE
				"0010" WHEN nA2='0' ELSE
				"0001" WHEN nA1='0' ELSE
				"0000";

 O3	<=	output(3);
 O2	<=	output(2);
 O1	<=	output(1);
 O0	<=	output(0);

END a;