-- 7-Segment Decoder with active low outputs, Lamp Test, Blanking, and Ripple Blanking LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY seven_seg IS PORT( Ain, Bin, Cin, Din, nLT, nBI, nRBI : IN STD_LOGIC; na, nb, nc, nd, ne, nf, ng, nRBO : OUT STD_LOGIC); END seven_seg; ARCHITECTURE decoder OF seven_seg IS SIGNAL input: STD_LOGIC_VECTOR (3 DOWNTO 0); SIGNAL output: STD_LOGIC_VECTOR (6 DOWNTO 0); BEGIN -- Concurrent signal assignment input (0) <= Ain; input (1) <= Bin; input (2) <= Cin; input (3) <= Din; display: PROCESS (input, nRBI, nBI, nLT) BEGIN -- If Statement IF (input = "0000" and nRBI ='0') THEN -- Blank leading 0 output <= "1111111"; nRBO <= '0'; ELSIF (input = "0000" and nRBI = '1') THEN -- display 0 output <= "0000001"; nRBO <= '1'; ELSE CASE input IS WHEN "0001" => output <= "1001111"; --display 1 WHEN "0010" => output <= "0010010"; --display 2 WHEN "0011" => output <= "0000110"; --display 3 WHEN "0100" => output <= "1001100"; --display 4 WHEN "0101" => output <= "0100100"; --display 5 WHEN "0110" => output <= "0100000"; --display 6 WHEN "0111" => output <= "0001111"; --display 7 WHEN "1000" => output <= "0000000"; --display 8 WHEN "1001" => output <= "0000100"; --display 9 WHEN "1010" => output <= "0001000"; --display A WHEN "1011" => output <= "1100000"; --display B WHEN "1100" => output <= "0110001"; --display C WHEN "1101" => output <= "1000010"; --display D WHEN "1110" => output <= "0110000"; --display E WHEN "1111" => output <= "0111000"; --display F WHEN others => output <= "1111111"; --blank END CASE; nRBO <= '1'; END IF; IF (nBI='0') THEN -- override DCBA and blank the display output <= "1111111"; END IF; IF (nLT='0') THEN -- override DCBA and lamp test. output <= "0000000"; END IF; na <= output(6); nb <= output(5); nc <= output(4); nd <= output(3); ne <= output(2); nf <= output(1); ng <= output(0); END PROCESS display; END decoder;