-- stopw.vhd
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;

ENTITY stopw IS
	PORT(       
        clk			: IN    STD_LOGIC;
        start, stop, lap 	: IN    STD_LOGIC;
		q		: OUT   INTEGER RANGE 0 TO 63);
END stopw;

ARCHITECTURE a OF stopw IS
	BEGIN
	PROCESS (clk)
	    VARIABLE    freqd	: INTEGER RANGE 0 TO 33554431;
	    VARIABLE    cnt 	: INTEGER RANGE 0 TO 63;
	    VARIABLE    lapcnt 	: INTEGER RANGE 0 TO 63;
		VARIABLE    flag	: integer Range 0 to 1;

		BEGIN
		IF (clk'EVENT AND clk = '1') THEN
			freqd := freqd +1;
			IF (stop ='0') then flag :=0; end if;
			IF (start = '0') then cnt := 0; freqd := 0; flag :=1; end if;
			IF (freqd = 25175000) then
				if (flag =1) then cnt := cnt + 1; end if;
				if (cnt =60) then cnt := 0; end if;
				freqd := 0;
				end if;
			if (lap ='1') then
				q	<=	cnt;	lapcnt := cnt;
				else	
				q   <= lapcnt;	
				end if;
			end if;
		END PROCESS;
	END a;