;*****************************************************************************
; EL Display Panel (Finlux)
; Real-Time Video Generator
;
; Other Files Required : p30F2010.gld, p30f2010.inc
; Tools Used : MPLAB IDE : 7.xx
;
;*****************************************************************************
	.equ __30F2010, 1
	.include "p30f2010.inc"
;.............................................................................
; Configuration bits:
;.............................................................................
	config __FOSC, CSW_FSCM_OFF & XT_PLL16 	;16xPLL - 120MHz/30MIPs at 7.37MHz XTAL
;	config __FOSC, CSW_FSCM_OFF & XT_PLL4 	;4xPLL
;	config __FOSC, CSW_FSCM_OFF & XT 		;No PLL
	config __FWDT, WDT_OFF 					;Turn off Watchdog Timer
	config __FBORPOR, PBOR_ON & BORV_27 & PWRT_16 & MCLR_EN	;Set Brown-out Reset voltage and
	config __FGS, CODE_PROT_OFF 			;Set Code Protection Off
	
;.............................................................................
; Global Declarations:
;.............................................................................
	.global __reset 	;Label for first line of code.
	.global	__ICD2RAM	;Allows ICD2 to be used

;.............................................................................
; Variable Storage in Data space (beginning at 0x850)
;.............................................................................
		.section	.data
		.align	2
DotCtr: .space 2	;Video Clock
LineCtr: .space 2

;.............................................................................
; Constants stored in Program space
;.............................................................................
	.equ	VIDEO,#0	;PORT B Lines to Display
	.equ	HSYNC,#1	;15.96 KHz 
	.equ	VSYNC,#2	;61Hz
	.equ	DCLK,#3		;Dot Clock - 6MHz??

;.............................................................................
; Code Section in Program Memory
;.............................................................................
	.text ;Start of Code section

	__reset:
;Setup Stack for Calls in program memory
	mov		#__SP_init,W15
	mov		#__SPLIM_init, W0			;Initialize the Stack Pointer Limit Register
	mov 	W0, SPLIM
	nop
	bset	CORCON,#IF			;Select Integer mode for DSP Multiplier

;Setup Ports
	mov		#0xFF00,W1		;RB0-RB4=Output
	mov		W1,TRISB
	mov 	#0x003F,W0 		;Setup all analog pins for digital mode
	mov 	W0,ADPCFG

NextFrame:
	bset	LATB,#HSYNC		;One Tvclk period before VSYNC
	nop
	
	inc		EvenOdd

;Generate Vertical Sync
	bclr	LATB,#VSYNC
	bset	LATB,#VSYNC
	
	mov		#0x0100,W1
	mov		w1,LineCtr	;256 Lines to scan

NextLine:
	bset	LATB,#HSYNC		;One Tvclk period before VSYNC
	mov		#0x0100,W1
	mov		w1,DotCtr
	bclr	LATB,#VIDEO		;Start with video Off

NextDot:
	mov		DotCtr,w2
	mov		LineCtr,w3
	sub		w3,w2,w2
	bra		NZ,GoAhead
	bset	LATB,#VIDEO
GoAhead:
	bset	LATB,#DCLK
	bclr	LATB,#DCLK
	dec		DotCtr
	bra		NZ,NextDot

	bclr	LATB,#VIDEO

;At the end of each line, HSYNC goes low for 4 Tvlck cycles
GenerateHSync:
	bclr	LATB,#HSYNC		;H Sync Low for 4 clocks
	mov		#4,W1
	mov		W1,DotCtr
HSyncWait:
	bset	LATB,#DCLK
	bclr	LATB,#DCLK
	dec		DotCtr
	bra		NZ,HSyncWait

;Get and scan the next line, No VSYNC within a frame
	dec		LineCtr	
	bra		NZ,NextLine

;After 256th Line (HS), delay for 300uS to VS active edge
;At 30MIPS, 30 instructions=1uS, 9000=300uS
;300uS is 10000 instructions at 30 MIPS
	mov		#1000,W1
	mov		W1,DotCtr
EndDly:
	nop					;Loop consumes 9 clocks *1000
	nop
	nop
	nop
	nop
	nop
	nop	
	dec		DotCtr
	bra		NZ,EndDly
	goto	NextFrame

;--------End of All Code Sections--------------------------------------------
.end ;End of program code in this file