Vintage Digital PDP-8 Computers

The PDP-8 series of minicomputers was the first "affordable" minicomputer in a time when mainframes dominated computer departments everywhere. Often described as the "Model T" of the computer industry, this series of machines was responsible, more than any other machine, for the proliferation of computers into labs and institutions everywhere: at a starting price of about $18000 when introduced in 1965, this unit was affordable by many small institutions which could not afford a larger machine. The college where I teach had four units in the 1970s - before this the only options were incredibly expensive mainframes. And by 1973, the PDP8 was the best selling computer in the world.

Small boxes, compared to mainframes at least, minicomputers are about the size of a large microwave oven and in the 1960's and 1970's, were built from technology ranging from discrete transistors (for the earliest PDP-8 models built in the mid-1960's) to integrated circuits in later models.

My collection consists of two PDP-8's. The first, a PDP-8/F circa 1972, was built in the heyday of minicomputers. It features a "blinking light" front panel from which operators would enter programs. The second, a PDP/8A circa 1978, was built at the end of the minicomputer era at a time when "minis" were already being replaced with "micros" with similar, or superior, capabilities but at much lower cost.


Role of the PDP 8 in the history of the computer ...

The PDP-8 was truly the "Model T" of computers. Like the Model-T, it was not the first of it's kind, but was designed for inexpensive mass-production. And like the model-T, it was not designed for comfort: it "drove" just fine, but the comfort of the user was not a design concern!

Before I leave the "model T" analogy, consider that Ford built multiple models, with "T" being a huge success. The follow-up, which should have been "Model U" was actually named "Model A" ... oddly DEC did the same thing with the PDP-8, with the 8/A being the last model produced (one is outlined on this page).

As far as "value engineering" goes, the PDP-8 architecture was designed to be simple and easy to implement with standard TTL logic (the original 1965 PDP-8 used DTL logic but this was later upgraded). The machine featured a twelve-bit word which could store two six-bit ASCII characters in a single word (in those days, a "character" was six bits in length whereas nowadays we use a byte). With only eight basic instructions and only one real user register (an accumulator), the machine is about as "stripped down" as it gets! Even so, the machine did support a basic DMA scheme allowing fast memory access from an I/O device.

The eight instructions are very simple and include an AND instruction, Two's-complement ADD instruction, JUMP instructions, I/O instruction (the machine had a separate I/O bus similar to the Zilog Z-80), and a "Microcoded Operation" instruction. The Microcoded Operation instruction does not mean "microcoded" in the way it does today ... simply that each bit of the instruction specified an action that could be combined together: for example clearing, incrementing, and rotating the accumulator all in one instruction saving a good deal of programming instructions. A simple scheme, it did make for confusing assembly code since multiple instruction operations had to be specified on the same line (e.g. "CLA CLL" to clear the accumulator then clear the link {carry} bit).

Having only one register, most instructions used a memory reference as a second value - for example the AND instruction operates with the accumulator and one of 128 registers (0008 through 1778). Of the twelve bits available to encode this instruction, three specify the instruction, one specified direct or indirect memory access, one specifies the memory page to use (current or page zero), and seven bits specify the memory address. Memory addresses in page zero are not generic since address 0000 is reserved as the location for Interrupt Service Routines (ISRs), and addresses 00108 to 00178 are autoincrement registers when used indirectly (i.e. as pointers to data in memory). For those using modern micros, the basic idea of having most operations reference memory is found in the MOS 6502 and the PIC series of microcontrollers from Microchip which use a single working register and one of many registers in RAM, both the 6502 and the later PIC18F series have a "page zero" default for register access as well.

Being a twelve-bit machine, direct access was provided only to 4K of memory - to access memory up to 32K (the maximum for a PDP-8), a "field" register was used to access eight 4K pages of memory (a decade plus later, and in a similar but more unusual manner, Intel would add a segment register to the 8080 architecture to extend the addressing capabilities to 1MB, calling the new processor the 8086).

On a personal note, as a user of modern micros, I still find it fascinating how the architecture of all of these are grounded in old machines like this one!


PDP 8/F

This PDP-8/F machine was donated to my collection by John Clark, a (now retired) colleague who used these type of machines at the college in the 1970's. Built with technology contemporary to the late 1960s and early 1970s, the machine is built from relatively simple TTL logic chips (e.g. 7400-series chips, most of which are in 14 and 16-pin packages) and comes from an era when computers had large front panels with a plethora of switches allowing the user to enter programs directly from the panel into memory.

PDP 8f CPU

PDP 8/F Boards

PDP 8/F Board Configuration For those of you unfamiliar with a PDP-8 consider that this is a true minicomputer in an era before CPU chips existed. There is no CPU 'chip' but rather several printed-circuit boards containing hundreds of discrete logic IC's. This model was the fifth in the PDP-8 family and used larger printed circuit boards in a bus (Omnibus) allowing the addition of peripherals such as I/O boards, TTY interfaces, and more memory. The base machine was shipped with 4K or 8K ... this unit has 8K installed. In the photograph above the CPU boards are seen to the right while the boards on the left are the core memory unit. The diagram on the left shows the configuration of the cards in the twenty-slot backframe.

Programs were entered on the front panel using the toggle switches. A starting address was entered and the LOAD_ADDRESS switch depressed. Machine instructions were then entered one at a time and the DEPOSIT key pressed each time to enter them into memory. When the program was complete, the starting address was entered once again and the START key pressed to run the program. Many small programs were hand-assembled. Consider this small program from the Digital Equipment Corp. Small Computer Handbook, 1967:

  • Set the switches for location 00408 and press the LOAD_ADDRESS key to load the starting address for the program.
  • Enter the machine instruction 72008 and press DEPOSIT. This is the CLA instruction which clears the accumulator
  • Enter the machine instruction 70018 and press DEPOSIT. This is the IAC instruction which increments the accumulator
  • Press the DEPOSIT key twice more to enter this instruction two more times
  • Enter the machine instruction 74028 and press DEPOSIT. This is the HLT instruction which halts the machine
  • Set the switches for location 00408 again and press the START key to run the program.
After the program runs the accumulator will be found to have a value of 3 and the program counter will have incremented to 00458 as seen on the front panel. Larger programs would be saved to paper tape and loaded into the machine via a teletype unit, the primary I/O device for these machines.

View A Short Movie showing the stepping-through of the above program

Plans for this machine ...

This machine is essentially a perfect specimen of a late 1960's computer. Aside from minor repairs such as one cooling fan which suffered the effects of time no work is required on it! In keeping with a machine true to its day, I plan on running it solely with papertape. While disk drives existed at the time they were horrifically expensive and so before the mid 70's the preeminent storage method was indeed papertape, usually punched and read from the ASR-33 teletype used as a console for these computers. Adding an RX-01 eight-inch floppy to the system does not do it historical justice (especially an 8/F)! Other 'historically-correct' storage devices available at the time include DECTape magnetic tape storage and the DF32 disk file: a fixed-head fixed-disk. Still, given the cost of mass storage, paper tape was certainly the most popular and was the standard for distribution of software.

While I'd like an original teletype to be historically correct these are heavy (100lbs ++) and large (consuming 6 square feet of floor space) beasts and being mechanical they were somewhat prone to frequent repairs (I had an old one given to me once, just the printer section, and it was indeed problematic).

The simpler (and more compact) option is to simply use a terminal emulator on a PC. I use Tera Term Pro which is free and runs under XP. Simply configure the package for 110 baud, No parity, 8 bits, 2 stop, and it is essentially a TTY terminal. The PC can keep a host of papertape images available for use and these can be uploaded as required. One of the links below has a host of tape images available including the OS/8 operating system and FOCAL calculator language.

Testing the Machine ...

Aside from the simple program above which increments the accumulator (a good for ensuring the system is running), the next test was to ensure the UART (called an Serial Line Unit or SLU by DEC) was running allowing upload of programming from the console. The M8650 asynchronous card in this machine is factory-preset for 110 baud only (an upgrade card, the -YA version, can handle various baud rates).

First, a BC-01 cable was built to allow the PDP to talk to a PC serial port. The M8650 is fitted with a 40-pin BERG connector - a cable was made as follows which adapts this connector (using a standard 40-pin 0.1" dual-row header) to a DB-9:

  • M8650 BERG Pin ( F ) to DB-9 Transmit (pin 2)
  • M8650 BERG Pin ( J ) to DB-9 Receive (pin 3)
  • M8650 BERG Pin ( E ) to M8650 BERG Pin ( M )
  • M8650 BERG Pin ( V V ) to DB-9 Ground (pin 5)
The M8650 card can operate with either a 20mA TTY current loop interface or an EIA (RS-232) interface depending on which jumpers are added to the BERG connector. My original cable was configured to work with a TTY hence why this cable was required.

Second, a simple (hand assembled) program was written as follows to test the UART:

7470/ 7200 CLA clear AC
7471/ 7001 IAC increment AC - now contains 0001
7472/ 7002 BSW byte swap AC - now contains 0100
7473/ 7001 IAC increment AC - now contains 0101 (65 dec)
7474/ 6046 TLS transmit AC via UART
7475/ 7402 HLT halt

Since the PDP-8 lacks a 'Load Accumulator with Constant' instruction the accumulator is first cleared with the CLA instruction and the accumulator incremented (IAC) so that the 12-bit accumulator now contains 00018 (We are working in octal here as per DEC standards). The High and Low six-bits of the accumulator are now swapped using the BSW instruction so that the accumulator has the value 01008 (This instruction is similar to the Microchip PIC 'swapf' instruction). Another increment instruction (IAC) leaves the accumulator with the value 01018 - in binary this is 000001000001 or 65 decimal - the ASCII code for the 'A' character. Finally, the contents of the accumulator are transmitted by the UART using the TLS instruction and the processor is halted. The program is loaded at 74708 - just below the location where many bootstrap loaders normally reside (see below). When the program is single-stepped and the front-panel set to display AC (accumulator), the operation of each instruction becomes evident ... and if all is working an 'A' appears on the PC which is running a terminal program such as TeraTerm (set to 110 baud, N, 8, 1).

Software ...

Papertape Program

Papertape came in two formats, RIM (Read-In Mode) and binary mode, both of which required a loader resident in memory. RIM mode is the simplest and uses four bytes for each memory entry - two for address and two for data. A typical RIM entry might look (in HEX) like:

40 01 2C 03 40 02 2C 03 40 03 15 03

Entries with bit 6 set (i.e. 0x40) signify an address field so the first two bytes are interpreted as Address 0001. The next two bytes are data. In binary these are 00101100 00000011 (2C 03). Stripping the top two bits of each byte and converting to octal the data becomes 54038 which is a jump command.

In order to read RIM tapes a loader is required which reads bytes from the ASR33 teletype and places these in memory using indirect addressing. The loader (taken from a DEC Small Computer Handbook), with addresses in the left column and my disassembly comments added, is as follows:

7756/ 6032 KCC clear AC and keyboard/reader flag
7757/ 6031 KSF skip if keyboard/reader flag = 1
7760/ 5357 JMP within this memory page (1) address 157 (absolute 7757, above)
7761/ 6036 KRB clear AC, read keyboard buffer, clear keyboard flag
7762/ 7106 CLL RTL clear link, rotate 2 left
7763/ 7006 RTL rotate AC and link left two
7764/ 7510 SPA skip on plus AC
7765/ 5357 JMP to memory page 1 address 157 (absolute 7757)
7766/ 7006 RTL rotate AC and link left two
7767/ 6031 KSF skip if keyboard/reader flag = 1
7770/ 5367 JMP within this memory page (1) address 167 (absolute 7767, above)
7771/ 6034 KRS read keyboard/reader buffer, static
7772/ 7420 SNL skip on non-zero link
7773/ 3776 DCA deposit and clear AC indirect memory page 1, address [7776]
7774/ 3376 DCA deposit and clear AC memory page1, address 176 (absolute 7776)
7775/ 5356 JMP within this memory page (1) address 156 (absolute 7756)

The user is required to manually enter the loader using the front-panel switches. It is located at address 7756 - the top of the last page in the first 4K of memory (which is all many machines were shipped with at the time). Having core memory, the loader stays in memory until overwritten.

It is instructive to examine how it works so here's a quick synopsis:
Retrieve a byte from the UART (KRB instruction). Rotate two bits left three times (7762, 7763, 7766) putting the lowest six bits received into the upper-six of the 12-bit word of this machine. A second retrieve (KRS 7771) receives the lower six bits so that a complete 12-bit word is received. At 7772 a decision is made to check if the received word is an address (bit 6 set in the first byte of the address) or data. If bit 6 (now in the link - what we commonly call the CARRY bit nowadays) ==0 (i.e. it is not an address) then deposit the received word into address pointed-to by 7776 by an indirect memory reference. If link ==1 it is an address word so deposit the received word into location 7776.

One of the most popular applications of the time (used in labs everywhere as a scientific calculator ... remember, people were still using slide rules at the time!) was FOCAL for FOrmula CALculator which came in both RIM and binary format. In RIM format the tape is 15.6KBytes in length. Although this takes twenty minutes to load, the machine has core memory which retains contents even when power is removed. This machine currently runs FOCAL '69. To load it the RIM loader above was keyed-in the front panel, the address set to 77568, and the loader program RUN on the PDP-8. The PCs terminal emulator ackage is then used to send the RIM file in binary format to the PDP. It is evident that the PDP is loading the 'tape' since the front-panel lights blink rapidly. Once uploaded (a _long_ process at 110 baud) he PDP-8 is restarted by enter the starting address of the FOCAL program now in memory (02008) on the front panel, loading that address, and RUN the program already there. Being a core-based machine, the program will reside there indefinitely and so may be used at any time without reloading. Other programs available on paper tape (most of which run on a 4K machine) include a FORTRAN compiler and utilities as well as a number of mathematical utilities such as double-precision math routines.

FOCAL '69 in RIM format as used in this test. This program is Copyright DEC, 1969, and was made available, courtesy of DEC, from Highgates PDP-8 page (see the links below). Be sure to download it in binary format.

PDP 8/A-400

A member of the last PDP-8 series built, this PDP-8/A 400 came from Tom MacDonald, a part-time colleague at the college. In another life, this machine operated an X-ray system and performed data acquisition and collection in a laboratory.

PDP-8/A Computer System The CPU has two operator panels: the limited-function panel on the bottom with only three switches (allowing powering of the system and booting) and the console on top allowing entry and examination of memory and processor state. This machine, circa 1978, is a later version of the classic PDP-8 minicomputer with similar functions to my the PDP-8/F but considerably updated.

Even the look of the machine is modern resembling that of a mid-1970's PDP-11 instead of the traditional orange-and-yellow look of a late-60's or early 70's PDP-8.

One might note that the PDP-8 lineage dates back to the mid-1960's and this is one of the last PDP-8's built ... with an address space of 32K, a 12-bit datapath, and 1.5uS cycle times, the writing was on the wall and microprocessors were rapidly overtaking processors built from discrete components like this one - fifteen years is a LONG time for a processor design to survive.

PDP 8/A Console
Where the 8/F features a plethora of switches on the front panel allowing the entry of addresses and data words, this updated interface has a keypad and seven-segment display. Memory addresses are loaded in octal via the keypad and displayed on the seven-segment LED display. Memory may be examined as well as written (deposited) allowing entry of programs such as bootstraps for loading programs from I/O devices and disks. Processor state may also be interrogated via the console.

PDP 8/A Cards The CPU is built using discrete integrated circuits and comes on three boards - the top three in this case (M8315, M8317, and M8316). The M8316 is a multifunction I/O card which combines functions found on multiple boards on earlier systems including the serial line unit, real time clock, parallel I/O, and console interface.

Below the CPU is a core memory unit consisting of G850 and H2198 boards connected together as a stack.

Removed from the CPU is a non-DEC interface board for the tape unit and the X-ray unit - the entire subsystem for the X-ray system was non-DEC, and was removed from the system.

Testing the Serial Line Unit

The first step was to ensure the serial line unit (UART) was functioning. DIP switches on the 8316 board were checked and the board was configured for 300 baud, one stop bit (For a D revision etch the switch settings are 0101111010 for switches 10....1 with a 1 being an ON). A BC-08 EIA cable was used to connect the SLU to a PC directly, the cable being identical to that used on te PDP-8/F above. A simple test program for the SLU, found in the user's manual, was keyed into the machine at 02008 as follows:

    7001 ;0200 IAC - Increment AC
    6046 ;0201 Transmit AC via SLU
    6041 ;0202 Skip if Transmit flag is set
    5202 ;0203 Jump -1
    5200 ;0204 Jump to 0200

When run, this simple program prints all characters from 0 to 3778 (0xFF in hex) on the terminal so that 'A' to 'Z' and all other ASCII characters are printed, along with a host of control characters (you know it has hit character 7 when it beeps!). The unit passed that test.